[Cialug] Masters and Slaves

[Zachary Kotlarek]

On Nov 2, 2008, at 7:03 PM, Colin Burnett wrote:

> Yeah, still different layers.  You're talking "IP address" and I'm
> talking "MAC address".  Ethernet doesn't care about IPs and however
> the ends interpret that IP is irrelevant to ethernet frame routing.


I'm not disagreeing that they're differing layers, I'm just saying  
they're both included in the layer that would commonly be called  
"SATA". Yes, the low-level signaling protocol used by SATA is point-to- 
point and addressless, but the overall SATA specification includes  
addressing for multiplexed links.


> Does anyone make a gigabit *hub*?


I'm pretty sure collision detection is still in the spec, but I've  
never seen a gigibit switch.


> I believe firewire and USB are also P2P with addressing done at a
> higher layer, yes?  Both are bidirectional serial streams.


FireWire is hostless and auto-assigns IDs after each bus reset. It can  
be run as a shared bus or in a tree topology. It also supports a  
second level of addressing that allows individual busses to be bridged  
together and addressed as a combined network.


> It seems the industry has all but abandoned multiple access and
> parallel.  I suspect, however, the cycle will come back around and
> people will realize that you could reduce hardware by sharing wires
> and get 8 times the data if you send it on 8 different wires!  Wow!


I'm not so sure. One of the reasons we've gone to serial interfaces is  
they are not subject to the timing problems that come with trying to  
read 8 wires with 1 clock. In PCIe for example, you can run multiple  
serial channels (or as PCIe calls them "lanes"), but they each have  
their own clock, and there's no need to synchronize the data among the  
channels (at least at a signaling level).

There's also the issue of signaling errors. Serial cables are much  
easier to shield from each other and from outside EM sources, and  
because it doesn't require additional cabling many high-speed serial  
protocols now include fairly robust forward error correction. PCIe for  
example encodes 10 bits to every 8 data bits, allowing recovery from  
signaling errors that do occur without rejecting the frame. With  
parallel data access you'd have to add even more wires -- SCSI cables  
already have 68 pins, and I doubt anyone wants to add 8 more for error  
correction.

Finally there's the issue of simultaneous inter-node communication. In  
high-speed devices the PCIe "bus" is implemented with a crossbar-like  
switching system, so that any two PCIe lanes can be connected to each  
other and can communicate at the same time as other PCIe nodes on  
other channels. Obviously this isn't useful in all applications, but  
when it is there are significant speed and latency advantages, and  
it's simply too many wires to switch if you're using a non-serial  
connection.

	Zach

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